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Computer Organization & Architecture

Computer Organization and Architecture is one of the most numerical GATE CS subjects. These lessons explain how a CPU executes instructions, how pipelines and caches make it fast, and how it talks to memory and devices, with small simulators for Booth multiplication, pipelines and caches, so every cycle count and hit count shown is computed.

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1Basics

  1. Computer Basics and PerformanceThe stored-program (von Neumann) computer, the CPU's registers and the instruction cycle, measuring performance with CPI, MIPS and execution time, and Amdahl's law.

2Instructions

  1. Instruction Sets and FormatsWhat an instruction contains, 3-, 2-, 1- and 0-address machines, fixed and variable instruction formats, field-width calculations, expanding opcodes, and RISC versus CISC.
  2. Addressing ModesHow an instruction finds its operand: immediate, register, direct, indirect, register indirect, indexed, base, PC-relative and auto-increment modes, effective-address calculations and memory reference counts.

3Arithmetic

  1. The ALU and MultiplicationWhat the ALU does, status flags, shift operations, shift-and-add multiplication, Booth's algorithm for signed multiplication with a full trace, the number of additions and subtractions it needs, and division.

4Processor Design

  1. Data Path and Control UnitRegister transfers and micro-operations, a single-bus data path and the control steps of an instruction, hardwired versus microprogrammed control, horizontal and vertical microinstructions, and control-memory size calculations.

5Pipelining

  1. Instruction PipeliningHow a pipeline overlaps instructions, the classic five stages, clock period with unequal stages and latches, total time for n instructions, speedup, efficiency and throughput.
  2. Pipeline HazardsStructural, data and control hazards, RAW, WAR and WAW dependences, stalls and operand forwarding, the load-use hazard, branch penalties and their effect on CPI, and a pipeline simulator that counts stalls.

6Memory

  1. Memory Hierarchy and Cache MappingLocality and the memory hierarchy, hit ratio and average memory access time, direct-mapped, fully associative and set-associative caches, splitting an address into tag, index and offset, and tag memory size.
  2. Cache Replacement, Writes and Access PatternsReplacement policies (LRU, FIFO, optimal), write-through and write-back with write-allocate options, the cost of writes, and how row-major versus column-major loops change the number of cache misses.
  3. Main Memory and Secondary StorageSRAM and DRAM, refresh, building a memory from smaller chips, address decoding, memory interleaving, and disk capacity and access time.

7Input/Output

  1. I/O, Interrupts and DMAI/O interfaces and ports, programmed I/O, interrupt-driven I/O, vectored and prioritised interrupts, daisy chaining, direct memory access in burst and cycle-stealing modes, and calculating the CPU time each method costs.

8GATE Practice

  1. COA GATE Practice SetMixed GATE-style questions on performance, instruction formats, addressing, Booth multiplication, microprogramming, pipelining and hazards, caches, memory design and DMA.