Latches and Flip-Flops

A sequential circuit has memory: its outputs depend on the inputs and on its current state, which is stored in flip-flops. In a synchronous circuit the state changes only at clock edges, so everything stays in step.

The SR latch

Two cross-coupled NOR gates store one bit. Inputs S (set) and R (reset):

A NAND version has active-low inputs (S′ R′ = 00 is the invalid case).

Level- versus edge-triggering

• A latch is level-sensitive: while its enable (clock) is high, the output follows the inputs. Inputs that change during that time pass straight through.
• A flip-flop is edge-triggered: it samples its inputs only at the clock edge (rising or falling) and holds the result for the whole cycle. This makes synchronous design predictable.

The four flip-flops

JK truth table:

The same behaviour as a state diagram, with the two states Q = 0 and Q = 1 (X = either value):

Excitation tables

To design a circuit, we know the transition we want (Q → Q⁺) and need the inputs that cause it. X means "don't care".

The many don't cares make JK flip-flops convenient for design by K-map.

def jk(q, j, k):
    return (j & (1 - q)) | ((1 - k) & q)

def t_ff(q, t):
    return q ^ t

q, trace = 0, []
for j, k in [(1, 0), (0, 0), (1, 1), (1, 1), (0, 1), (1, 1)]:
    q = jk(q, j, k)
    trace.append(q)
print("JK, starting at Q = 0:", trace)

q, trace = 1, []
for t in [1, 1, 0, 1, 0, 0, 1]:
    q = t_ff(q, t)
    trace.append(q)
print("T, starting at Q = 1: ", trace)

JK, starting at Q = 0: [1, 1, 0, 1, 0, 1]
T, starting at Q = 1:  [0, 1, 1, 0, 0, 0, 1]

Race-around

In a level-triggered JK latch with J = K = 1, the output toggles, feeds back, and toggles again, as long as the clock stays high: it oscillates, and the final value is unpredictable. This is the race-around condition. It occurs when the clock pulse is longer than the propagation delay. Fixes: a master–slave JK flip-flop (the master samples while the clock is high, the slave copies it when the clock goes low) or an edge-triggered flip-flop.

Converting one flip-flop into another

Use the excitation table of the available flip-flop to express its inputs in terms of the desired flip-flop's inputs and Q:

• JK from D: D = JQ′ + K′Q (the JK characteristic equation).
• T from JK: J = K = T.
• D from JK: J = D, K = D′.
• T from D: D = T ⊕ Q.
• D from T: T = D ⊕ Q.

Timing

• Setup time t_su: the input must be stable this long before the clock edge.
• Hold time t_h: it must stay stable this long after the edge.
• Propagation delay t_pd (clock-to-Q): how long after the edge the output changes.

Between two flip-flops with combinational logic in between, the clock period must allow a signal to leave one flip-flop, pass through the logic and settle before the next edge:

T_clk ≥ t_pd + t_comb + t_su, so f_max = 1 / (t_pd + t_comb + t_su).

Practice questions